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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 july 1994 integrated circuits philips semiconductors TDA9150b programmable deflection controller
july 1994 2 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b features general 6.75, 13.5 and 27 mhz clock frequency few external components synchronous logic i 2 c-bus controlled easy interfacing low power esd protection flash detection with restart two-level sandcastle pulse. vertical de?ection self adaptive 16-bit precision vertical scan dc coupled deflection to prevent picture bounce programmable fixed compression to 75% s-correction can be preset s-correction setting independent of the field frequency differential output for high dc stability current source outputs for high emc immunity programmable de-interlace phase. east-west correction dc coupled ew correction to prevent picture bounce 2nd and 4th order geometry correction can be preset trapezium correction geometry correction settings are independent of field frequency self adaptive bult generator prevents ringing of the horizontal deflection current source output for high emc immunity. horizontal de?ection phase 2 loop with low jitter internal loop filter dual slicer horizontal flyback input soft start by i 2 c-bus over voltage protection/detection with selection and status bit. eht correction input selection between aquadag or eht bleeder internal filter. general description the TDA9150b is a programmable deflection controller contained in a 20-pin dip package and constructed using bimos technology. this high performance synchronization and dc deflection processor has been especially designed for use in both digital and analog based tv receivers and monitors, and serves horizontal and vertical deflection functions for all tv standards. the TDA9150b uses a line-locked clock at 6.75, 13.5 or 27 mhz, depending on the line frequency and application, and requires only a few external components. the device is self-adaptive for a number of functions and is fully programmable via the i 2 c-bus. ordering information type number package pins pin position material code TDA9150b 20 dip plastic sot146-1
july 1994 3 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b quick reference data notes 1. hard wired to ground or v cc is highly recommended. 2. dac values: vertical amplitude = 31; eht = 0; shift = 3; scor = 0. symbol parameter conditions min. typ. max. unit v cc supply voltage 7.2 8.0 8.8 v i cc supply current f clk = 6.75 mhz - 27 - ma p tot total power dissipation - 220 - mw t amb operating ambient temperature - 25 - +70 c inputs v 14 line-locked clock (llc) logic level - ttl - v 13 horizontal sync (h a ) logic level - ttl - v 12 vertical sync (v a ) logic level - ttl - v 5 line-locked clock select (llcs) logic level note 1 - cmos 5 v - v 18 serial clock (scl) logic level - cmos 5 v - v 17 serial data input (sda) logic level - cmos 5 v - v psl horizontal ?yback (hfb) phase slicing level fbl = logic 0 - 3.9 - v fbl = logic 1 - 1.3 - v v 1 horizontal ?yback (hfb) blanking slicing level - 100 - mv v 3 over voltage protection (prot) level - 3.9 - v v 9 eht ?ash detection level - 1.5 - v outputs v 20 horizontal output (hout) voltage (open drain) i 20 = 10 ma -- 0.5 v i 11 - i 10(m) vertical differential (vout a, b ) output current (peak value) vertical amplitude = 100%; i 8 = - 120 m a; note 2 440 475 510 m a v 10,11 vertical output voltage 0 - 3.9 v i 6(m) ew (ewout) total output current (peak value) i 8 = - 120 m a -- 930 m a v 6 ew (ewout) output voltage 1.0 - 5.5 v s andcastle output levels (dsc) v 2 base voltage level - 0.5 - v v 2 horizontal and vertical blanking voltage level - 2.5 - v v 2 video clamping voltage level - 4.5 - v h orizontal off - centre shift ( ofcs ) v 19 output voltage i 19 = 2 ma 0 - v cc v
july 1994 4 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b block diagram fig.1 block diagram.
july 1994 5 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b pinning symbol pin description hfb 1 horizontal ?yback input dsc 2 display sandcastle input/output prot 3 over voltage protection input agnd 4 analog ground llcs 5 line-locked clock selection input ewout 6 east-west geometry output eht 7 eht compensation r conv 8 external resistive conversion flash 9 ?ash detection input vout b 10 vertical output b vout a 11 vertical output a v a 12 vertical information input h a 13 horizontal information input llc 14 line-locked clock input dgnd 15 digital ground v cc 16 supply input (+8 v) sda 17 serial data input/output scl 18 serial clock input ofcs 19 off-centre shift output hout 20 horizontal output fig.2 pin configuration. functional description input signals (pins 12, 13, 14, 17 and 18) the TDA9150b requires three signals for minimum operation (apart from the supply). these signals are the line-locked clock (llc) and the two i 2 c-bus signals (sda and scl). without the llc the device will not operate because the internal synchronous logic uses the llc as the system clock. i 2 c-bus transmissions are required to enable the device to perform its required tasks. once started the ic will use the h a and/or v a inputs for synchronization. if the llc is not present the outputs will be switched off and all operations discarded (if the llc is not present the line drive will be inhibited within 2 m s, the ew output current will drop to zero and the vertical output current will drop to 20% of the adjusted value within 100 m s). the sda and scl inputs meet the i 2 c-bus specification, the other three inputs are ttl compatible. the llc frequency can be divided-by-two internally by connecting llcs (pin 5) to ground thereby enabling the prescaler. the llc timing is given in the chapter characteristics.
july 1994 6 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b i 2 c-bus commands slave address: 8c hex = 1000110x bin read mode the format of the status byte is: pon prot 000000 where: pon is the status bit for power-on reset (por) and after power failure: logic 1: C after the first por and after power failure; also set to 1 after a severe voltage dip that may have disturbed the various settings C por 1 to 0 transition, v cc = 6.25 v (typ.) C por 0 to 1 transition, v cc = 5.75 v (typ.) logic 0: C after a successful read of the status byte. prot is the over voltage detection for the scaled eht input: logic 1: C if the scaled eht rises above the reference value of 3.9 v logic 0: C after a successful read of the status byte and eht < 3.9 v. remark : a read action is considered successful when an end of data signal has been detected (i.e. no master acknowledge). table 1 write mode with auto increment; subaddress and data byte format. notes 1. x = dont care. 2. data bit used in another function. function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 vertical amplitude 00 x (1) x a5a4a3a2a1a0 vertical s-correction 01 x x a5 a4 a3 a2 a1 a0 vertical start scan 02 x x a5 a4 a3 a2 a1 a0 vertical off-centre shift 03 x note 2 note 2 note 2 x a2 a1 a0 ew trapezium correction 03 x a6 a5 a4 x note 2 note 2 note 2 ew width/width ratio 04 x x a5 a4 a3 a2 a1 a0 ew parabola/width ratio 05 x x a5 a4 a3 a2 a1 a0 ew corner/parabola ratio 06 x x a5 a4 a3 a2 a1 a0 eht compensation 07 x x a5 a4 a3 a2 a1 a0 horizontal phase 08 x x a5 a4 a3 a2 a1 a0 horizontal off-centre shift 09 x x a5 a4 a3 a2 a1 a0 clamp shift 0a x xxxxa2a1a0 control 1 0b ms ws fbl vap blds lfss dint gbs control 2 0f x x x vpr cpr dip prd csu
july 1994 7 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b table 2 control bits. control bit logic function lfss 0 line stop: ew output current becomes zero and the vertical output current is reduced to 20% of the adjusted value. lfss becomes logic 0 after a high on pon. 1 line start enabled: the soft start mechanism is now activated. dint 0 de-interlace on: the v a pulse is sampled at a position selected with control bit dip. 1 de-interlace off: the v a pulse is sampled with the system clock and the detected rising edge is used as vertical reset. blds 0 aquadag selected. 1 bleeder selected. gbs 0 becomes logic 0 after power-on. 1 guard band 48/12 lines. vap 0 positive v a edge detection. 1 negative v a edge detection. fbl 0 horizontal ?yback slicing level = 3.9 v. 1 horizontal ?yback slicing level = 1.3 v. csu 0 no clamping suppression, standard mode of operation. 1 clamping suppression in wait, stop and protection modes (used in systems with e.g. tda4680/81). prd 0 no defeat of hout, the over voltage information is only written in the prot status bit. 1 hout is defeated and status bit prot is set when over voltage is detected. dip 0 v a is sampled 42 clock pulses after the leading edge of h a . 1v a is sampled 258 clock pulses after the leading edge of h a . cpr 0 nominal amplitude. 1 compression to 75% of adjusted amplitude, used for display of 16 : 9 standard pictures on 4 : 3 displays. vpr 0 nominal amplitude (100%) during wait, stop and clipping. 1 amplitude reduced to 20% during wait, stop and clipping.
july 1994 8 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b table 3 explanation of control bits shown in table 2. table 4 clock frequency control bit (pin 5; note 1). note 1. switching of the prescaler is only allowed when lfss is low. it is highly recommended to hard wire llcs to ground or v cc . active switching may damage the output power transistor due to the changing hout pulse. this may cause very high currents and large flyback pulses. the permitted combinations of llc and the prescaler are shown in table 5. table 5 line duration with prescaler. note 1. combination not allowed. control bits description lfss line frame start/stop dint de-interlace blds bleeder mode selection gbs guard band selection vap polarity of v a edge detection fbl ?yback slicing level csu clamping suppression mode prd protection/detection mode dip de-interlace phase cpr compression on/off vpr vertical power reduction mode control bit logic function llcs 0 prescaler on: the internal clock frequency f clk = 1 2 f llc 1 prescaler off (default by internal pull-up resistor): the internal clock frequency f clk = f llc llc (mhz) on ( m s) off ( m s) 6.75 note 1 64 13.5 64 32 27 32 note 1
july 1994 9 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b fig.3 timing relations between llc, h a and line counter.
july 1994 10 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b horizontal part (pins 1, 2, 13, 19 and 20) s ynchronization pulse the h a input (pin 13) is a ttl-compatible cmos input. pulses on this input have to fulfil the timing requirements as illustrated in fig.6. for correct detection the minimum pulse width for both the high and low periods is 2 internal clock periods. f lyback input pulse the hfb input (pin 1) is a cmos input. the delay of the centre of the flyback pulse to the leading edge of the h a pulse can be set via the i 2 c-bus with the horizontal phase byte (subaddress 08), as illustrated in fig.7. the resolution is 6-bit. o utput pulse the hout pulse (pin 20) is an open-drain nmos output. the duty factor for this output is typically 52 48 (conducting/non-conducting) during normal operation. a soft start causes the duty factor to increase linearly from 5 to 52% over a minimum period of 2000 lines in 2000 steps. o ff - centre shift the ofcs output (pin 19) is a push-pull cmos output which is driven by a pulse-width modulated dac. by using a suitable interface, the output signal can be used for off-centre shift correction in the horizontal output stage. this correction is required for hdtv tubes with a 16 9 aspect ratio and is useful for high performance flat square tubes to obtain the required horizontal linearity. for applications where off-centre correction is not required, the output can be used as an auxiliary dac. the ofcs signal is phase-locked with the line frequency. the off-centre shift can be set via the i 2 c-bus, subaddress 09, with a 6-bit resolution as illustrated in fig.8. s andcastle the dsc input/output (pin 2) acts as a sandcastle generating output and a guard sensing input. as an output it provides 2 levels (apart from the base level), one for the horizontal and vertical blanking and the other for the video clamping. as an input it acts as a current sensor during the vertical blanking interval for guard detection. c lamping pulse the clamping pulse width is 21 internal clock periods. the shift, with respect to h a can be varied from 35 to 49 clock periods in 7 steps via the i 2 c-bus, clamp shift byte subaddress 0a, as illustrated in fig.9. it is possible to suppress the clamping pulse during wait, stop and protection modes with control bit csu. this will avoid unwanted reset of the tda4680/81 (only used in those circuits). h orizontal blanking the start of the horizontal blanking pulse is minimum 38 and maximum 41 clock periods before the centre of the flyback pulse, depending on the f clk /f h ratio k in accordance with 41 - (432 - k). stop of the horizontal blanking pulse is determined by the trailing edge of the hfb pulse at the horizontal blanking slicing level crossing as illustrated in fig.10. v ertical blanking the vertical blanking pulse starts two internal clock pulses after the rising edge of the v a pulse. during this interval a small guard pulse, generated during flyback by the vertical power output stage, must be inserted. stop vertical blanking is effected at the end of the blanking interval only when the guard pulse is present (see section vertical guard). the start scan setting determines the end of vertical blanking with a 6-bit resolution in steps of one line via the i 2 c-bus subaddress 02 (see figs 11 and 12). v ertical guard in the vertical blanking interval a small unblanking pulse is inserted. this pulse must be filled-in by a blanking pulse or guard pulse from the vertical power output stage which was generated during the flyback period. in this condition the sandcastle output acts as guard detection input and requires a minimum 800 m a input current. this current is sensed during the unblanking period. vertical blanking is only stopped at the end of the blanking interval when the inserted pulse is present. in this way the picture tube is protected against damage in the event of missing or malfunctioning vertical deflection (see figs 11 and 12).
july 1994 11 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b vertical part (pins 6, 8, 10, 11 and 12) s ynchronization pulse the v a input (pin 12) is a ttl-compatible cmos input. pulses at this input have to fulfil the timing requirements as illustrated in fig.6. for correct detection the minimum pulse width for both the high and low period is 2 internal clock periods. for further requirements on minimum pulse width see also section de-interlace. v ertical place generator with control bit cpr a compress to 75% of the adjusted values is possible in all modes of operation. this control bit is used to display 16 : 9 standard pictures on 4 : 3 displays. no new adjustment of other corrections, such as corner and s-correction, is required. with control bit vpr a reduction of the current during clipping, wait and stop modes to 20% of the nominal value can be selected, which will reduce the dissipation in the vertical drive circuits. the vertical start-scan data (subaddress 02) determines the vertical placement in the total range of 64 432 clock periods in 63 steps. the maximum number of synchronized lines per scan is 910 with an equivalent field frequency of 17.2 or 34.4 hz for f h = 15625 or 31250 hz respectively. the minimum number of synchronized lines per scan is 200 with an equivalent field frequency of 78 or 156 hz for f h = 15 625 or 31250 hz respectively. if the v a pulse is not present, the number of lines per scan will increase to 910.2. if the llc is not present the vertical blanking will start within 2 m s. amplitude control is automatic, with a settling time of 1 to 2 new fields and an accuracy of either 16/12 or 48/12 lines depending on the value of the gbs bit. differences in the number of lines per field, as can occur in txt or in multi-head vtr, will not affect the amplitude setting providing the differences are less than the value selected with gbs. this is called amplitude control guardband. the difference sequence and the difference sequence length are not important. d e - interlace with de-interlace on (dint = logic 0), the v a pulse is sampled with llc at a position supplied by control bit dip (de-interlace phase). when dip = logic 0 sampling takes place 42 clock pulses after the leading edge of h a (t = t line 42/432). when dip = logic 1 sampling takes place 258 clock pulses after the leading edge of h a (t = t line 258/432). the distance between the two selectable sampling points is (t line (258 - 42)/432) which is exactly half a line, thus de-interlace is possible in two directions. the duration of the v a pulse must, therefore, be sufficient to enable the h a pulse to caught, in this event an active time of minimum of half a line (see fig.13 which has an integration time of t line 1 4 for the v a pulse). with de-interlace off, the v a pulse is sampled with the system clock. the leading edge is detected and used as the vertical reset. selection of the positive or negative leading edge is achieved by the control bit vap. v ertical geometry processing the vertical geometry processing is dc-coupled and therefore independent of field frequency. the external resistive conversion (r conv ) at pin 8 sets the reference current for both the vertical and ew geometry processing. a useful range is 100 to 150 m a, the recommended value is 120 m a. vertical outputs the vertical outputs vout a and vout b on pins 10 and 11 together form a differential current output. the vertical amplitude can be varied over the range 80 to 120% in 63 steps via the i 2 c-bus (subaddress 00). vertical s-correction is also applied to these outputs and can be set from 0 to 16% by subaddress 01 with a 6-bit resolution. the vertical off-centre shift (ofcs) shifts the vertical deflection current zero crossing with respect to the ew parabola bottom. the control range is - 1.5 to +1.5% ( 1 8 i 8 ) in 7 steps set by the least significant nibble at subaddress 03.
july 1994 12 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b ew geometry processing the ew geometry processing is dc coupled and therefore independent of field frequency. r conv sets the reference current for both the vertical and ew geometry processing. the ew output is an esd-protected single-ended current output. the ew width/width ratio can be set from 100 to 80% in 63 steps via subaddress 04 and the ew parabola/width ratio from 0 to 20% via subaddress 05. the ew corner/ew parabola ratio has a control range of - 40 to 0% in 63 steps via subaddress 06. the ew trapezium correction can be set from - 1.5 to +1.5% in 7 steps via the most significant nibble at subaddress 03. bult generator the bult generator makes the ew waveform continuous (see fig.20). protection input (pin 3) the protection input (prot) is a cmos input. the input voltage must be eht scaled and has the following characteristics: two modes of protection are available with the aid of control bit prd. with prd = logic 1 the protection mode is selected, hout will be defeated and the prot bit in the status word is set if the input voltage is above 3.9 v. thus the deflection stops and ew output current is zero, while the vertical output current is reduced to 20% of the adjusted value. a new start of the circuit is i 2 c-bus controlled with the user software. with prd = logic 0 the detection mode is selected, hout will not be defeated and the over voltage information is only written in the prot status bit and can be read by the i 2 c-bus. all further actions, such as a write of the lfss bit, are achieved by the i 2 c-bus. they depend on the configuration used and are defined by user software. flash detection/protection input (pin 9) the flash input is a cmos input with an internal pull-up current of approximately 8 m a. when a negative-going edge crosses the 0.75 v level a restart will be executed with a soft start of approximately 2000 lines, such as in the soft-start mode. when the function is not used pin 9 can be connected to ground, v cc or left open-circuit, the internal pull-up current source will prevent any problems. however a hard wired connection to v cc or ground is recommended when the function is not used. eht compensation (pin 7) the eht input is a cmos input. the eht compensation input permits scan amplitude modulation should the eht supply not be perfect. for correct tracking of the vertical and horizontal deflection the gain of the ew output stage, provided by the ratio r conv-ew /r conv , must be 1 16 v scan v ref (see fig.14). the input for eht compensation can be derived from an eht bleeder or from the picture tubes aquadag (subaddress 0b, bit blds). eht compensation can be set via subaddress 07 in 63 steps allowing a scan modulation range from - 10 to +9.7%.
july 1994 13 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b internal circuitry handbook, full pagewidth 300 w 1 2 300 w 3 4 300 w 5 6 mbd863 300 w 7 8 300 w 9 10 300 w 14 15 16 300 w 17 300 w 18 19 20 300 w 13 300 w 12 11 TDA9150b fig.4 internal circuitry.
july 1994 14 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b application information handbook, full pagewidth mbd864 c95 c89 22 m f 100 nf v cc ( 8 v) sda 100 w r75 scl 100 w r76 1 k w r77 TDA9150b v cc ( 8 v) hout ofcs 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 llc h v a a r99 3.3 k w c97 100 nf v cc ( 8 v) 4.7 k w 39 k w eht flash detection input r87 r88 3.3 k w r84 15 k w r85 hfb 23 v (peak) dsc 1 2 3 4 5 6 7 8 9 10 11 12 13 r113 r117 1 2 3 330 w r113 c105 100 m f 100 nf 16 v (vert) c105 100 m f 45 v (vert) tda8350 r107 82 k w zener diode c110 100 nf 33 v ew-out vertical deflection coil lv 3 k w r105 ie5 ie5 fig.5 application diagram.
july 1994 15 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b timing diagrams fig.6 timing requirements for llc, h a and v a . nnnnnnn nnnnnnn fig.7 horizontal phase and hout control range.
july 1994 16 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b fig.8 ofcs duty factor. fig.9 dsc clamping pulse.
july 1994 17 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b fig.10 dsc line blanking. fig.11 dcs vertical blanking with unblanking.
july 1994 18 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b fig.12 dsc with guard interval; start scan = 24. vertical blanking low period: during scan, during unblanking. vertical blanking high period (2.5 v): during stsc. vertical blanking continuously high: por = logic 1, lfss = logic 0, no guard detected.
july 1994 19 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b fig.13 de-interlace timing. i = start v a for dint = logic 1. d = start v a for dint = logic 0. fig.14 explanation of r conv-ew /r conv ratio.
july 1994 20 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b limiting values in accordance with the absolute maximum rating system (iec134). note 1. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. thermal characteristics symbol parameter min. max. unit v cc supply voltage - 0.5 8.8 v i cc supply current - 10 +50 ma p tot total power dissipation - 500 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - 25 +70 c v supply voltage supplied to pins 1 to 3, 5 to 14 and 17 to 20 - 0.5 v cc + 0.5 v i i/o current in or out of any pin except pins 4, 15 and 16 - 20 +20 ma v esd electrostatic handling for all pins (note 1) - 2000 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 70 k/w
july 1994 21 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b characteristics v cc = 8v;t amb = 25 c; dgnd = agnd = 0 v; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cc supply voltage 7.2 8.0 8.8 v i cc supply current note 1; f clk = 6.75 mhz - 27 - ma p tot total power dissipation - 220 - mw v por power-on reset por 1-to-0 transition - 6.25 7.0 v por 0-to-1 transition 5.0 5.75 - v sda and scl (pins 17 and 18) v 17 sda input voltage 0 - 5.5 v v il low level input voltage (pin 17) -- 1.5 v v ih high level input voltage (pin 17) 3.5 -- v i il low level input current (pin 17) v 17 = v ssd --- 10 m a i ih high level input current (pin 17) v 17 = v cc -- 10 m a v ol low level output voltage (pin 17) i il = 3 ma -- 0.4 v v 18 scl input voltage 0 - 5.5 v v il low level input voltage (pin 18) -- 1.5 v v ih high level input voltage (pin 18) 3.5 -- v i il low level input current (pin 18) v 18 = v ssd --- 10 m a i ih high level input current (pin 18) v 18 = v cc -- 10 m a line-locked clock and line-locked clock select (pins 14 and 5) v il low level input voltage (pin 14) -- 0.8 v v ih high level input voltage (pin 14) 2.0 -- v i 14 input current v 14 = < 5.5 v - 10 - +10 m a t r rise time 0 - 1 2 t llc t f fall time 0 - 1 2 t llc d 0 duty factor llcs = logic 0; at 1.4 v; note 2 40 50 60 % d 1 duty factor llcs = logic 1; at 1.4 v; note 2 25 50 75 % t iming ( prescaler on ;f clk = 1 2 f llc where f clk = internal clock ) f llc line-locked clock frequency 12.4 - 29.2 mhz k line-locked clock frequency ratio between f llc and f h h locked 856 864 865 h unlocked - 866 - line-locked clock frequency ratio between f clk and f h h locked 428 432 432.5 h unlocked - 433 -
july 1994 22 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b t iming ( prescaler off ;f clk =f llc where f clk = internal clock ) f llc line-locked clock frequency 6.2 - 15.5 mhz k line-locked clock frequency ratio between f llc and f h h locked 428 432 432 h unlocked - 433 - line-locked clock frequency ratio between f clk and f h h locked 428 432 432 h unlocked - 433 - v 5 llcs input voltage 0 - 8.8 v v il low level input voltage (pin 5) -- 1.5 v v ih high level input voltage (pin 5) 3.5 -- v i il low level input current (pin 5) v 5 = v ssd --- 150 m a i ih high level input current (pin 5) v 5 = v cc -- 100 m a horizontal part i nput signals h a (pin 13) v il low level input voltage -- 0.8 v v ih high level input voltage 2.0 -- v i 13 input current v 13 = 5.5 v - 10 - +10 m a t r rise time 0 - 1 2 t llc ns t f fall time 0 - 1 2 t llc ns t wh pulse width high 2 t clk -- t wl pulse width low 2 t clk -- hfb (pin 1) v psl phase slicing level fbl = logic 0 3.7 3.9 4.1 v fbl = logic 1 1.1 1.3 1.5 v v blank blanking slicing level 0 0.1 0.2 v i 1 input current - 10 - +10 m a horizontal phase (delay centre ?yback pulse to leading edge of h a ; where n = horizontal phase data) cr control range 0 n t clk n + (432 - k) t clk number of steps - 63 - o utput signals hout (pin 20) v 20 output voltage i 20 = 0 0 - v cc v v ol low level output voltage i 20 = 10 ma -- 0.5 v i 20 input current output off - 10 - +10 m a d duty factor normal operation 51 52 53 % symbol parameter conditions min. typ. max. unit
july 1994 23 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b soft start (duty factor controlled line drive) t w initial pulse width soft start -- 5% cr control range 5 - 53 % t ss soft start time 1500 - 3000 lines switch-off time to the centre of the ?yback pulse cr control range note 3 0 - 160 - (432 - k) t clk f control sensitivity (loop gain) 400 1000 -m s/ m s k correction factor note 4 - 0.5 - s sigma value of phase jitter note 5 - 750 - ps psrr power supply rejection ratio -- 10 ns/v horizontal off-centre shift (pin 19; n = off-centre shift data) v 19 output voltage 0 - v cc v v ol low level output voltage i 19 = 2 ma -- 0.5 v v oh high level output voltage i 19 = - 2ma v cc - 0.5 -- v d (max) maximum duty factor n < 54 1/k (8n + 1)/k 425/k % d duty factor n 3 54 - 1 - % number of steps - 54 - s andcastle ( pin 2) dsc output voltage v clamp video clamping voltage 4.0 4.5 5.0 v v blank horizontal and vertical blanking voltage level 2.0 2.5 3.0 v v base base voltage level 0 0.5 1.0 v i 2 output current guard not detected - 1.0 - +0.35 ma guard detected 0.8 - 2.5 ma t r rise time - 60 - ns t f fall time - 60 - ns clamping pulse (n = clamp pulse shift data) t w clamping pulse width - 21 t clk - t clamp clamp pulse shift w.r.t h a 35 (2n + 35) t clk 49 number of steps - 7 - t start start of horizontal blanking before middle of ?yback pulse 38 41 - (432 - k) t clk 41 symbol parameter conditions min. typ. max. unit
july 1994 24 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b vertical blanking width (n = vertical start-scan data) cr control range 1 432t clk (n + 1) 432t clk 64 432t clk k = 432 1 - 64 lines number of steps - 63 - guard detection (n = vertical start-scan data) t start start interval w.r.t v a no wait {48(n+1) +2} t clk -- t stop stop interval w.r.t v a no wait {96(n+1) +2} t clk -- vertical section input signals ( pin 12; v a ) v il low level input voltage -- 0.8 v v ih high level input voltage 2.0 -- v i 12 input current v 12 < 5.5 v - 10 - +10 m a t r rise time 0 - 1 2 t llc t f fall time 0 - 1 2 t llc t wh pulse width high 2 t clk -- t wl pulse width low 2 t clk -- t wh pulse width high de-interlace mode 0.5 t line -- t wl pulse width low de-interlace mode 0.5 t line -- vertical place generator (n = vertical start-scan data) cr control range 1 432t clk (n + 1) 432t clk 64 432t clk k = 432 1 - 64 lines number of steps - 63 - l max maximum number of synchronized lines per scan - 910 - lines/ scan f eq equivalent ?eld frequency at 910 lines/scan f h = 15625 hz - 17.2 - hz f h = 31250 hz - 34.4 - hz l min minimum number of synchronized lines per scan - 200 - lines/ scan f eq equivalent ?eld frequency at 200 lines/scan f h = 15625 hz - 78 - hz f h = 31250 hz - 156 - hz ca amplitude control - automatic - ca g amplitude control guardband gbs = logic 0 - 16/12 - lines gbs = logic 1 - 48/12 - lines settling time 1 1.5 2 new ?elds symbol parameter conditions min. typ. max. unit
july 1994 25 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b vertical geometry processing d i (m) vertical differential output current between vout a and vout b (peak value) v a = 100%; note 6; i 8 = - 120 m a 440 475 510 m a d/ d t drift over temperature range -- 10 - 4 k - 1 amplitude error due to s-correction setting -- 2% 1 2 (i 10 +i 11 ) vertical output signal bias current i 8 = - 120 m a 275 325 375 m a i os vertical output offset current note 7 -- 1% os/ d t offset over temperature range -- 10 - 4 k - 1 v 10 vertical output voltage (pin 10) 0 - 3.9 v v 11 vertical output voltage (pin 11) 0 - 3.9 v cmrr common mode rejection ratio -- 1 %/v le linearity error adjacent blocks; note 8 -- 2.0 % non-adjacent blocks; note 8 -- 3.0 % vertical amplitude (n = vertical amplitude data) cr control range note 9 81 - 119 % number of steps - 63 - vertical s-correction (n = s-correction data) cr control range note 9 0 - 15 % number of steps - 63 - vertical shift cr control range - 1 8 i 8 - + 1 8 i 8 m a number of steps - 7 - ew output (pin 6) v 6 output voltage note 10 1.0 - 5.5 v i 6 output current i 8 = - 120 m a; note 11 15 - 930 m a rr output ripple rejection - 0.15 1 %/v d/ d t output drift over temperature range -- 5.10 - 4 k - 1 ew width / width ratio cr control range note 9 100 - 81 % i eq equivalent output current 15 - 440 m a number of steps - 63 - symbol parameter conditions min. typ. max. unit
july 1994 26 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b ew parabola / width ratio cr control range note 9 1 - 19 % i eq equivalent output current width = 100% 10 - 430 m a width = 80% 10 - 345 m a number of steps - 63 - ew corner / ew parabola ratio cr control range notes 9 and 12 40 - 0% i eq equivalent output current width = 100% 0 - 200 m a width = 80% 0 - 160 m a number of steps - 63 - ew trapezium correction ew trapezium/width ratio note 9 - 1.5 - +1.5 % number of steps - 7 - eht input (pin 7) v ref reference voltage blds = logic 1 - 3.9 - v blds = logic 0 - v cc - v v i input voltage w.r.t v ref blds = logic 1 - 20 0 +20 % v i input voltage w.r.t v cc blds = logic 0 0 -- 2v ref v m scan scan modulation - 10 0 +9.7 % m gc modulation gain control 0 - 1 number of steps - 63 - i i input current - 100 - +100 na r conv input (pin 8) v o output voltage i 8 = - 120 m a 3.7 3.9 4.1 v i 8 current range - 100 - 120 - 150 m a prot input (pin 3) v i input voltage 0 - v cc v v 3 voltage detection level 3.7 3.9 4.1 v i i input current - 10 - +10 m a flash detection input (pin 9) v i input voltage 0 - v cc v v 9 voltage detection level falling edge 0.5 0.75 1.0 v h detection level hysteresis 0.3 0.5 0.8 v i 9 detection pull-up current - 4 - 8 - 16 m a symbol parameter conditions min. typ. max. unit
july 1994 27 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b notes to the characteristics 1. for all other frequencies the expected supply current will be as shown in table 6 (f clk is the internal clock frequency, f llc is the internal clock frequency applied to pin 14). 2. when the prescaler is on, one in two llc high periods is omitted. 3. for 16 khz operation the minimum value of the control range is 5.7 m s. with 1 2 t fb = 5.7 m s the minimum storage time is 0 and the maximum is 18 m s. for 32 khz operation the minimum value of the control range is 0 m s. with 1 2 t fb = 2.85 m s the minimum storage time is 0 and the maximum is 9 m s. 4. the k factor is defined as the amount of correction of a phase step. thus with k = 0.5 a 50% correction of the error takes place each line. the resulting step response now becomes k n , with n the line number after the step. 5. the sigma value ( s ) of the jitter with respect to llc at f h = 32 khz and a storage time of 5 m s. measurement of s is carried out during 200 lines in the active scan, the resulting peak-to-peak value is approximately 6 s . the visible jitter on the screen will be higher than the peak-to-peak jitter, depending on the deflection stage. 6. dac values: vertical amplitude = 31; eht = 0; shift = 3; scor = 0. 7. value is a percentage of i 10 - i 11 . 8. the linearity error is measured without s-correction and based on the same measurement principle as used for the screen. measuring method: divide the output signal i 10 - i 11 into 22 equal parts, ranging from 1 to 22 inclusive. measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). thus part 1 and 22 are unused. linearity error for adjacent blocks = linearity error for non-adjacent blocks = where a = amplitude, a k = amplitude block k and a avg = average amplitude. 9. minimum available range. 10. selection of test mode. when the ew output is pulled above v cc - 0.5 v a special test mode is entered in which the prescaler and the clock detector are disabled. 11. dac values: vertical amplitude = 31; eht = 0; width = 0. 12. the value of - 40% (typically 46%) corresponds with data 3f (hexadecimal) and implies maximum 4th order compensation. table 6 supply current with prescaler on/off. note 1. combination not allowed. llc (mhz) on (ma) off (ma) 6.75 note 1 27 13.5 27 38 27 42 note 1 a k a k1 + () C a avg ----------------------------- - a max a min C a avg ----------------------------- -
july 1994 28 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b test and application information fig.15 control range amplitude. i 11 - i 10 . fig.16 control range s-correction. bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbb
july 1994 29 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b fig.17 control range ew parabola/width ratio. bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbb fig.18 control range ew corner/ew parabola ratio.
july 1994 30 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b bbbbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbbbb fig.19 control range ew width. fig.20 the bult makes the ew waveform continuous. bbbbbbbbbbbbbbbbbbbbbbbbb bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbb b bbbbbbbbbbbbbbbbbbbbbbbbb
july 1994 31 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b package outline fig.21 plastic dual in-line package; 20 leads (300 mil); dip20, sot146-1. dimensions in mm. msa258 2.54 (9x) 0.254 m 0.53 max seating plane 3.60 3.05 2.0 max 26.92 26.54 4.2 max 3.2 max 0.51 min 8.25 7.80 0.38 max 7.62 10.0 8.3 11 10 6.40 6.22 1.73 max 20 1 soldering plastic dual in-line packages b y dip or wave the maximum permissible temperature of the solder is 260 c; this temperature must not be in contact with the joint for more than 5 s. the total contact time of successive solder waves must not exceed 5 s. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). if its temperature is below 300 c, it must not be in contact for more than 10 s; if between 300 and 400 c, for not more than 5 s.
july 1994 32 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
july 1994 33 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b notes
july 1994 34 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b notes
july 1994 35 philips semiconductors preliminary speci?cation programmable de?ection controller TDA9150b notes
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. 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(02)6752.3302, fax. (02)6752 3300. japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: philips components, 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)14163160/4163333, fax. (01)14163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., components division, 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (081)73050000, fax. (081)7548421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd33 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 533061/1500/01/pp36 date of release: july 1994 document order number: 9397 737 80011

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